1. Field of the Invention
The present invention relates to a circuit for switching between asynchronous clocks. In particular, the present invention relates to a circuit for glitchless switching between asynchronous clocks.
2. Background of the Related Art
The dynamic switching between multiple clock sources is an operation required by several kinds of applications.
The operation of computers, for instance, is based on the selection of several clock sources so as to optimize at the same time both the performances and the power consumption of the system. Applications requiring high performances of the system components such as the processor of the computer will be accordingly managed by high frequencies clock signals thereby requiring high power consumption. On the contrary, applications which can be run with reduced power consumption without affecting the quality of the results will be managed with low frequency signals.
Another example of applications involving the dynamic switching between multiple clock sources concerns the video technology wherein high definition modes (HD) and standard definition modes (SD) are managed by corresponding HD and SD clock signals having different frequencies.
One of the main problems related to the switching between multiple clock sources concerns the formation of glitches, i.e. transient pulses, in the output signal at the switching instant. Examples of glitches are spike pulses or clock periods shorter than the pulses of fastest clock source between the multiplicity of clock sources present in the system.
Glitches are particularly undesirable because they may cause critical instabilities in the entire system. In particular, the presence of glitches may cause undefined states for the system which can ultimately lead to crashes and serious damages of the system.
In order to remove glitches, solutions have been proposed based on the concept of glitch check management. In particular, these solutions are based on the application of detection and filtering circuits for detecting the presence of glitches in the relevant signal and for filtering them out. Nevertheless, these solutions require complicated architectures which are accordingly expensive and difficult to implement. Moreover, these solutions do not provide a satisfactory solution for the above problem because the filtering may not allow for the complete removal of the glitches.
Given these problems with the existing technology, it would be advantageous to provide a system which allows the output of glitchless signals, at the same time dispensing with the need for glitch check management.